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LTC3207/LTC3207-1
APPLICATIONS INFORMATION
V BAT , CPO Capacitor Selection
The style and value of the capacitors used with the LTC3207/
LTC3207-1 determine several important parameters such
as regulator control loop stability, output ripple, charge
pump strength and minimum start-up time.
To reduce noise and ripple, it is recommended that low
equivalent series resistance (ESR) ceramic capacitors are
used for both C VBAT and C CPO . Tantalum and aluminum
capacitors are not recommended due to high ESR.
The value of C CPO directly controls the amount of output
ripple for a given load current. Increasing the size of C CPO
will reduce output ripple at the expense of higher start-up
current. The peak-to-peak output ripple of the 1.5x mode
is approximately given by the expression:
V RIPPLEp ? p = I OUT
3 f OSC ? C CPO
Where f OSC is the LTC3207/LTC3207-1’s oscillator fre-
quency, or typically 850kHz, and C CPO is the output stor-
age capacitor.
The output ripple in 2x mode is very small due to the fact
that load current is supplied on both cycles of the clock.
Both style and value of the output capacitor can signi?-
cantly affect the stability of the LTC3207/LTC3207-1. As
shown in the Block Diagram, the device uses a control
the required output current. The error signal of the loop is
stored directly on the output capacitor. The output capacitor
also serves as the dominant pole for the control loop. To
prevent ringing or instability, it is important for the output
capacitor to maintain at least 3.2μF of capacitance over all
conditions and the ESR should be less than 80mΩ.
Multilayer ceramic chip capacitors typically have exception-
al ESR performance. MLCCs combined with a tight board
layout will result in very good stability. As the value of C CPO
controls the amount of output ripple, the value of C VBAT
controls the amount of ripple present at the input pin(V BAT ).
The LTC3207/LTC3207-1’s input current will be relatively
constant while the charge pump is either in the input charg-
ing phase or the output charging phase but will drop to zero
during the clock nonoverlap times. Since the nonoverlap
time is small (~25ns), these missing “notches” will result
in only a small perturbation on the input power supply
line. Note that a higher ESR capacitor such as tantalum
will have higher input noise due to the higher ESR. There-
fore, ceramic capacitors are recommended for low ESR.
Input noise can be further reduced by powering the
LTC3207/LTC3207-1 through a very small series inductor
as shown in Figure 4. A 10nH inductor will reject the fast
current notches, thereby presenting a nearly constant-
current load to the input power supply. For economy, the
10nH inductor can be fabricated on the PC board with
about 1cm (0.4") of PC board trace.
loop to adjust the strength of the charge pump to match
V BAT
LTC3207/
LTC3207-1
GND
3207 F04
Figure 4. 10nH Inductor Used for Input Noise Reduction
(Approximately 1cm of Board Trace)
3207fc
15
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